Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines

This paper describes the design of a totally self-checking signature analysis checker to be used to implement self-checking finite state machines. The application of the signature analysis method is studied taking into account trade off criteria concerning area and timing constraints requested in specific applications. In this paper, we propose a novel VHDL realization of this methodology suitable for the implementation of the SSMM for satellite applications described in [1][2]. Finally, we will present a general criterion to evaluate the optimal solution in terms of area overhead between the proposed method and a typical duplication and compare strategy.